Mr. Puneet Gupta

Chip Design Considerations for High Performance Computing

Abstract:

High Performance Computing (HPC) demands chip designs that deliver exceptional speed, scalability, and energy efficiency. This presentation explores the key architectural and physical design considerations necessary to meet these requirements. It covers the use of heterogeneous compute architectures, advanced process nodes (5nm and below), power and thermal optimization techniques, and robust clocking strategies. Emphasis is placed on interconnect design (e.g., HBM, PCIe, NoC), chiplet-based integration, and the use of AI-driven automation for PPA (Performance, Power, Area) optimization. Furthermore, the talk outlines the importance of signoff accuracy, reliability under variation, and scalable design flows to support next-generation HPC workloads. The objective is to provide actionable insights into building chips that are not only high-performing but also power-aware, scalable, and manufacturable at scale.

Profile:

Experienced and results-driven ASIC/SoC Physical Design Engineer with over 19 years of proven expertise across leading semiconductor companies, spanning technology nodes from 16nm to 3nm. Highly skilled in full-flow physical implementation—covering synthesis, floorplanning, custom clock tree design, power planning, routing, and timing closure. Demonstrated leadership in delivering complex, high-performance, and low-power designs, including CPUs, GPUs, AI accelerators, DDR PHYs, and special cores. Proficient in advanced STA, IR/EMIR, crosstalk, and signoff methodologies using industry-standard EDA tools. Adept at vendor management, team leadership, and flow automation, with strong customer-facing and cross-functional collaboration skills.