Mr. Puneet Gupta

Chip for AI & AI for Chips

Abstract:

As Artificial Intelligence (AI) continues to reshape industries, the semiconductor world is undergoing a parallel transformation. This talk explores the dual dynamic of “Chips for AI” — how cutting-edge semiconductor technologies are enabling AI at scale — and “AI for Chips” — how AI is revolutionizing the chip design and manufacturing process itself. As a physical design engineer with hands-on experience in advanced process nodes and design automation, I will share real-world insights into high-performance AI chip architectures, AI-powered EDA tools, and the co-evolution of compute and intelligence. The session will also discuss industry trends, challenges in power, performance, and area (PPA) optimization, and how AI is enabling faster tapeouts and smarter silicon.  

Profile:

Experienced and results-driven ASIC/SoC Physical Design Engineer with over 19 years of proven expertise across leading semiconductor companies, spanning technology nodes from 16nm to 3nm. Highly skilled in full-flow physical implementation—covering synthesis, floorplanning, custom clock tree design, power planning, routing, and timing closure. Demonstrated leadership in delivering complex, high-performance, and low-power designs, including CPUs, GPUs, AI accelerators, DDR PHYs, and special cores. Proficient in advanced STA, IR/EMIR, crosstalk, and signoff methodologies using industry-standard EDA tools. Adept at vendor management, team leadership, and flow automation, with strong customer-facing and cross-functional collaboration skills.